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CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
Integrated Device Technology, Inc.
IDT72401 IDT72402 IDT72403 IDT72404
FEATURES:
* * * * * * * * * * * * * * * * * * First-ln/First-Out Dual-Port memory 64 x 4 organization (IDT72401/03) 64 x 5 organization (IDT72402/04) IDT72401/02 pin and functionally compatible with MMI67401/02 RAM-based FIFO with low falI-through time Low-power consumption -- Active: 175mW (typ.) Maximum shift rate -- 45MHz High data output drive capability Asynchronous and simultaneous read and write Fully expandable by bit width Fully expandable by word depth IDT72403/04 have Output Enable pin to enable output data High-speed data communications applications High-performance CMOS technology Available in CERDIP, plastic DIP and SOIC Military product compliant to MlL-STD-883, Class B Standard Military Drawing #5962-86846 and 5962-89523 is listed on this function. Industrial temperature range (-40C to +85C) is available, tested to military electrical specifications
DESCRIPTION:
The IDT72401 and IDT72403 are asynchronous highperformance First-ln/First-Out memories organized 64 words by 4 bits. The IDT72402 and IDT72404 are asynchronous high-performance First-ln/First-Out memories organized as 64 words by 5 bits. The IDT72403 and IDT72404 also have an
Output Enable (OE) pin. The FlFOs accept 4-bit or 5-bit data at the data input (D0-D3, 4). The stored data stack up on a firstin/first-out basis. A Shift Out (SO) signal causes the data at the next to last word to be shifted to the output while all other data shifts down one location in the stack. The Input Ready (IR) signal acts like a flag to indicate when the input is ready for new data (IR = HIGH) or to signal when the FIFO is full (IR = LOW). The Input Ready signal can also be used to cascade multiple devices together. The Output Ready (OR) signal is a flag to indicate that the output remains valid data (OR = HIGH) or to indicate that the FIFO is empty (OR = LOW). The Output Ready can also be used to cascade multiple devices together. Width expansion is accomplished by logically ANDing the Input Ready (IR) and Output Ready (OR) signals to form composite signals. Depth expansion is accomplished by tying the data inputs of one device to the data outputs of the previous device. The Input Ready pin of the receiving device is connected to the Shift Out pin of the sending device and the Output Ready pin of the sending device is connected to the Shift In pin of the receiving device. Reading and writing operations are completely asynchronous allowing the FIFO to be used as a buffer between two digital machines of widely varying operating frequencies. The 45MHz speed makes these FlFOs ideal for high-speed communication and controller applications. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
SI IR D0-3 D4 (IDT72402 and IDT72404) MR DATA IN INPUT CONTROL LOGIC WRITE POINTER WRITE MULTIPLEXER Q 0-3 Q 4 (IDT72402 and IDT72404) OUTPUT CONTROL LOGIC SO OR
2747 drw 01
OUTPUT ENABLE
OE (IDT72403 and IDT72404)
MEMORY ARRAY
DATA OUT
MASTER RESET
READ MULTIPLEXER READ POINTER
The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
SEPTEMBER 1996
DSC-2747/7
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IDT72401, IDT72402, IDT72403, IDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT72401/IDT72403 IDT72402/IDT72404 (IDT72404 Only)
NC/OE(1) IR SI D0 D1 D2 D3 GND
1 2 3 4 5 6 7 8
16 15
P16-1, D16-1 & S016-1
14 13 12 11 10 9
Vcc SO OR Q0 Q1 Q2 Q3 MR
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DIP/SOIC TOP VIEW
NC/OE(2) IR SI D0 D1 D2 D3 D4 GND
1 2 3 4 5 6 7 8 9
18 17 16
P18-1, D18-1 & S018-1
15 14 13 12 11 10
Vcc SO OR Q0 Q1 Q2 Q3 Q4 MR
2747 drw 03
DIP/SOIC TOP VIEW
OE NC IR SI D0 D1 D2 D3 D4 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Vcc NC SO OR Q0 Q1 Q2 Q3 Q4 MR
2747 drw 04
NOTES: 1. Pin 1: NC - No Connection IDT72401, OE - IDT72403 2. Pin 1: NC - No Connection IDT72402,OE - IDT72404
CERPACK TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Rating Terminal Voltage with Respect to GND Operating Temp. Temperature Under Bias Storage Temp. DC Output Current Commercial -0.5 to +7.0 Military -0.5 to +7.0 Unit V
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VCC GND VIH VIL
(1)
Parameter Mil. Supply Voltage Com'l. Supply Voltage Supply Voltage Input High Voltage Input High Voltage
Min. 4.5 4.5 0 2.0 --
Typ. 5.0 5.0 0 -- --
Max. Unit 5.5 5.5 0 -- 0.8 V V V V V
2747 tbl 02
TA TBIAS TSTG IOUT
0 to +70 -55 to +125 -55 to +125 50
-55 to +125 -65 to +135 -65 to +150 50
C C C mA
NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle.
NOTE: 2747 tbl 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 5 7 Unit pF pF
2747 tbl 03
NOTE: 1. This parameter is sampled and not 100% tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V 10%, TA = 0C to +70C; Military: VCC = 5.0V 10%, TA = -55C to +125C)
Symbol IIL IIH VOL VOH IOS IHZ ILZ ICC
(2,3) (1)
Parameter Low-Level Input Current High-Level Input Current Low-Level Output Voltage High-Level Output Voltage Output Short-Circuit Current Off-State Output Current (IDT72403 and IDT72404) Supply Current
Test Conditions VCC = Max., GND VI VCC VCC = Max., GND VI VCC VCC = Min., IOL = 8mA VCC = Min., IOH = -4mA VCC = Max., VO = GND VCC = Max., VO = 2.4V VCC = Max., VO = 0.4V VCC = Max., f = 10MHz Com'l. Military
Min. -10 -- -- 2.4 -20 -- -20 -- --
Max. -- 10 0.4 -- -110 20 -- 35 45
Unit A A V V mA A A mA mA
04
NOTES: 2747 tbl 1. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Guaranteed but not tested. 2. ICC measurements are made with outputs open. OE is HIGH for IDT72403/72404. 3 For frequencies greater than 10MHZ, ICC = 35mA + (1.5mA x [f - 10MHz]) commercial, and ICC = 45mA + (1.5mA x [f - 10MHz]) military.
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IDT72401, IDT72402, IDT72403, IDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING CONDITIONS
(Commercial: VCC = 5.0V 10%, TA = 0C to +70C; Military: VCC = 5.0V 10%, TA = -55C to +125C)
Commercial IDT72401L45 IDT72402L45 IDT72403L45 IDT72404L45 Min. Max. 9 11 0 13 9 11 20 10 3 13 0 -- -- -- -- -- -- -- -- -- -- -- IDT72401L35 IDT72402L35 IDT72403L35 IDT72404L35 Min. Max. 9 17 0 15 9 17 25 10 3 15 0 -- -- -- -- -- -- -- -- -- -- -- Military and Commercial IDT72401L25 IDT72401L15 IDT72402L25 IDT72402L15 IDT72403L25 IDT72403L15 IDT72404L25 IDT72404L15 Min. Max. Min. Max. 11 24 0 20 11 24 25 10 5 20 0 -- -- -- -- -- -- -- -- -- -- -- 11 25 0 30 11 25 25 25 5 30 0 -- -- -- -- -- -- -- -- -- -- -- IDT72401L10 IDT72402L10 IDT72403L10 IDT72404L10 Min. Max. 11 30 0 40 11 25 30 35 5 30 0 -- -- -- -- -- -- -- -- -- -- --
Symbol tSIH(1) tSIL tIDS tIDH tSOH(1) tSOL tMRW tMRS tSIR tHIR tSOR(4)
Parameters Shift in HIGH Time Shift in LOW TIme Input Data Set-up Input Data Hold Time Shift Out HIGH Time Shift Out LOW Time Master Reset Pulse Master Reset Pulse to SI Data Set-up to IR Data Hold from IR Data Set-up to OR HIGH
FIgure 2 2 2 2 5 5 8 8 4 4 7
Unit ns ns ns ns ns ns ns ns ns ns ns
2747 tbl 05
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V 10%, TA = 0C to +70C; Military: VCC = 5.0V 10%, TA = -55C to +125C)
Commercial IDT72401L45 IDT72402L45 IDT72403L45 IDT72404L45 Min. Max. -- -- -- -- -- -- 5 -- -- -- -- -- -- -- 9 9 45 18 18 45 18 19 -- 19 30 25 25 20 12 12 -- -- IDT72401L35 IDT72402L35 IDT72403L35 IDT72404L35 Min. Max. -- -- -- -- -- -- 5 -- -- -- -- -- -- -- 9 9 35 18 20 35 18 20 -- 20 34 28 28 20 15 12 -- -- Military and Commercial IDT72401L25 IDT72401L15 IDT72402L25 IDT72402L15 IDT72403L25 IDT72403L15 IDT72404L25 IDT72404L15 Min. Max. Min. Max. -- -- -- -- -- -- 5 -- -- -- -- -- -- -- 11 11 25 21 28 25 19 34 -- 34 40 35 35 25 20 15 -- -- -- -- -- -- -- -- 5 -- -- -- -- -- -- -- 11 11 15 35 40 15 35 40 -- 40 65 35 35 35 30 25 -- -- IDT72401L10 IDT72402L10 IDT72403L10 IDT72404L10 Min. Max. -- -- -- -- -- -- 5 -- -- -- -- -- -- -- 11 11 10 40 45 10 40 55 -- 55 65 40 40 40 35 30 -- --
Symbol tIN tIRL(1) tIRH
(1)
Parameters Shift In Rate Shift In to Input Ready LOW Shift In to Input Ready HIGH Shift Out Rate Shift Out to Output Ready LOW Shift Out to Output Ready HIGH Output Data Hold (Previous Word) Output Data Shift (Next Word) Data Throughput or "Fall-Through" Master Reset to OR LOW Master Reset to IR HIGH Master Reset to Data Output LOW Output Valid from OE LOW Output High-Z from OE HIGH Input Ready Pulse HIGH Ouput Ready Pulse HIGH
FIgure 2 2 2 5 5 5 5 5 4, 7 8 8 8 9 9 4 7
Unit MHz ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns
tOUT tORL(1) tORH tODH tODS tPT tMRORL tMRIRH tMRQ tOOE(3) tHZOE tIPH
(3,4) (2,4) (1)
tOPH(2,4)
NOTES: 2747 tbl 06 1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1F directly between VCC and GND with very short lead length is recommended. 2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs of like speed grades. 3. IDT72403 and IDT72404 only. 4. Guaranteed by design but not currently tested.
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IDT72401, IDT72402, IDT72403, IDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figure 1
2747 tbl 07
5V 560 OUTPUT 1.1K 30pF*
2747 drw 06
ALL INPUT PULSES:
3.0V GND
or equivalent circuit
90% 10% 90% 10%
<3ns
<3ns
2747 drw 05
Figure 1. AC Test Load *Including scope and jig
SIGNAL DESCRIPTIONS INPUTS:
DATA INPUT (D0-3, 4)
OUTPUTS:
DATA OUTPUT (Q0-3, 4) Data Output lines. The IDT72401 and IDT72403 have a 4bit data output. The IDT72402 and IDT72404 have a 5-bit data output.
Data input lines. The IDT72401 and IDT72403 have a 4-bit data input. The IDT72402 and IDT72404 have a 5-bit data input.
FUNCTIONAL DESCRIPTION
These 64 x 4 and 64 x 5 FIFOs are designed using a dual port RAM architecture as opposed to the traditional shift register approach. This FIFO architecture has a write pointer, a read pointer and control logic, which allow simultaneous read and write operations. The write pointer is incremented by the falling edge of the Shift In (Sl) control; the read pointer is incremented by the falling edge of the Shift Out (SO). The Input Ready (IR) signals when the FIFO has an available memory location; Output Ready (OR) signals when there is valid data on the output. Output Enable (OE) provides the capability of three-stating the FIFO outputs. FIFO Reset The FIFO must be reset upon power up using the Master Reset (MR) signal. This causes the FlFO to enter an empty state, signified by Output Ready (OR) being LOW and Input Ready (IR) being HIGH. In this state, the data outputs (Q0-3, 4) will be LOW. Data Input Data is shifted in on the LOW-to-HlGH transition of Shift In (Sl). This loads input data into the first word location of the FIFO and causes Input Ready to go LOW. On the HlGH-toLOW transition of Shift In, the write pointer is moved to the next word position and Input Ready (IR) goes HIGH, indicating the readiness to accept new data. If the FIFO is full, Input Ready will remain LOW until a word of data is shifted out.
CONTROLS:
SHIFT IN (SI) Shift In controls the input of the data into the FIFO. When SI is HIGH, data can be written to the FIFO via the D0-3, 4 lines. SHIFT OUT (SO) Shift Out controls the output of data of the FIFO. When SO is HIGH, data can be read from the FIFO via the Data Output (Q0-3, 4) lines. MASTER RESET (MR) Master Reset clears the FIFO of any data stored within. Upon power up, the FIFO should be cleared with a Master Reset. Master Reset is active LOW. INPUT READY (IR) When Input Ready is HIGH, the FIFO is ready for new input data to be written to it. When IR is LOW the FIFO is unavailable for new input data. Input Ready is also used to cascade many FlFOs together, as shown in Figures 10 and 11 in the Applications section. OUTPUT READY (OR) When Output Ready is HIGH, the output (Q0-3, 4) contains valid data. When OR is LOW, the FIFO is unavailable for new output data. Output Ready is also used to cascade many FlFOs together, as shown in Figures 10 and 11. OUTPUT ENABLE (OE) (IDT72403 AND IDT72404 ONLY) Output enable is used to read FIFO data onto a bus. Output Enable is active LOW.
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IDT72401, IDT72402, IDT72403, IDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Data Output Data is shifted out on the HlGH-to-LOW transition of Shift Out (SO). This causes the internal read pointer to be advanced to the next word location. If data is present, valid data will appear on the outputs and Output Ready (OR) will go HIGH. If data is not present, Output Ready will stay LOW indicating the FIFO is empty. The last valid word read from the FIFO will remain at the FlFOs output when it is empty. When the FIFO is not empty, Output Ready (OR) goes LOW on the LOW-to-HIGH transition of Shift Out. Previous data remains on the output until the HIGH-to-LOW transition of Shift Out (SO).
Fall-Through Mode The FIFO operates in a fall-through mode when data gets shifted into an empty FIFO. After a fall-through delay the data propagates to the output. When the data reaches the output, the Output Ready (OR) goes HIGH. Fall-through mode also occurs when the FIFO is completely full. When data is shifted out of the full FIFO, a location is available for new data. After a fall-through delay, the Input Ready goes HIGH. If Shift In is HIGH, the new data can be written to the FIFO. Since these FlFOs are based on an internal dual-port RAM architecture with separate read and write pointers, the fallthrough time (tPT) is one cycle long. A word may be written into the FIFO on a clock cycle and can be accessed on the next clock cycle.
TIMING DIAGRAMS
1/fIN SHIFT IN tSIH t SIL tIRH INPUT READY tIDH INPUT DATA tIDS
Figure 2. Input Timing
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1/fIN
tIRL
(7)
SHIFT IN
(1)
(2)
(4)
(5)
INPUT READY
(3)
(6)
INPUT DATA
STABLE DATA
2747 drw 08
NOTES: 1. Input Ready HIGH indicates space is available and a Shift In pulse may be applied. 2. Input Data is loaded into the first word. 3. Input Ready goes LOW indicating the first word is full. 4. The write pointer is incremented. 5. The FIFO is ready for the next word. 6. If the FIFO is full then the Input Ready remains LOW. 7. Shift In pulses applied while Input Ready is LOW will be ignored (see Figure 4). Figure 3. The Mechanism of Shifting Data Into the FIFO
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IDT72401, IDT72402, IDT72403, IDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
(2)
SHIFT OUT
(3)
SHIFT IN
(4)
(5)
INPUT READY
(1)
tPT t SIR
t IPH t HIR STABLE DATA
2747 drw 09
INPUT DATA
NOTES: 1. FIFO is initially full. 2. Shift Out pulse is applied. 3. Shift In is held HIGH. 4. As soon as Input Ready becomes HIGH the Input Data is loaded into the FIFO. 5. The write pointer is incremented. Shift In should not go LOW until (tPT + tIPH). Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH
1/fOUT SHIFT OUT tSOH t SOL
(2)
1/fOUT
tORH OUTPUT READY tODH tODS OUTPUT DATA A-DATA
(1)
tORL B-DATA C-DATA
2747 drw 10
NOTES: 1. This data is loaded consecutively A, B, C. 2. Data is shifted out when Shift Out makes a HIGH to LOW transition. Figure 5. Output TIming
SHIFT OUT
(7)
(2) (1)
(4)
OUTPUT READY
(3)
(5) (6)
OUTPUT DATA
A-DATA A or B
B-DATA
2747 drw 11
NOTES: 1. Output Ready HIGH indicates that data is available and a Shift Out pulse may be applied. 2. Shift Out goes HIGH causing the next step. 3. Output Ready goes LOW. 4. The read pointer is incremented. 5. Output Ready goes HIGH indicating that new data (B) is now available at the FIFO outputs. 6. If the FIFO has only one word loaded (A DATA) then Output Ready stays LOW and the A DATA remains unchanged at the outputs. 7. Shift Out pulses applied when Output Ready is LOW will be ignored. Figure 6. The Mechanism of Shifting Data Out of the FIFO
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IDT72401, IDT72402, IDT72403, IDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
SHIFT IN
SHIFT OUT tPT OUTPUT READY
(1)
t SOR DATA OUTPUT
t OPH DATA VALID
2747 drw 12
NOTE: 1. FIFO initially empty. Figure 7. tPT and tOPH Specification
-
t MRW MASTER RESET t MRIRH INPUT READY
(1) (1)
t MRORL
OUTPUT READY t MRS SHIFT IN t MRQ DATA OUTPUT
NOTE: 1. Worst case, FIFO initially full.. Figure 8. Master Reset Timing
2747 drw 13
OUTPUT ENABLE t HZOE DATA OUT
2747 drw 14
t OOE
NOTE: 1. High-Z transitions are referenced to the steady-state VOH -500mV and VOL +500mV levels on the output. tHZOE is tested with 5pF load capacitance instead of 30pF as shown in Figure 1. Figure 9. Output Enable Timing, IDT72403 and IDT72404 Only
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IDT72401, IDT72402, IDT72403, IDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APPLICATIONS
SHIFT IN INPUT READY DATA IN SI IR D0 D1 D2 D3 OR SO Q0 Q1 Q2 Q3 SI IR D0 D1 D2 D3 OR SO Q0 Q1 Q2 Q3 OUTPUT READY SHIFT OUT DATA OUT
MR
MR
2747 drw 15
MR
NOTE: 1. FIFOs can be easily cascaded to any desired path. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices. Figure 10. 128 x 4 Depth Expansion
IR SI D0 D1 D2 D3
MR
SO OR Q0 Q1 Q2 Q3
IR SI D0 D1 D2 D3
MR
SO OR Q0 Q1 Q2 Q3
IR SI D0 D1 D2 D3
MR
SO OR Q0 Q1 Q2 Q3
SHIFT OUT
COMPOSITE INPUT READY
IR SI D0 D1 D2 D3
MR
SO OR Q0 Q1 Q2 Q3
IR SI D0 D1 D2 D3
MR
SO OR Q0 Q1 Q2 Q3
IR SI D0 D1 D2 D3
MR
SO OR Q0 Q1 Q2 Q3
COMPOSITE OUTPUT READY
SHIFT IN
IR SI D0 D1 D2 D3
MR
SO OR Q0 Q1 Q2 Q3
IR SI D0 D1 D2 D3
MR
SO OR Q0 Q1 Q2 Q3
IR SI D0 D1 D2 D3
MR
SO OR Q0 Q1 Q2 Q3 MR
2747 drw 16
NOTES: 1. When the memory is empty, the last word will remain on the outputs until the Master Reset is strobed or a new data word falls through to the output. However, OR will remain LOW, indicating data at the output is not valid. 2. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays LOW until the new data has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs. 3. If SO is held HIGH while the memory is empty and a word is written into the input, that word will appear at the output after a fall-through time. OR will go HIGH for one internal cycle (at least tORL) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO, they will line up behind the first word and will not appear on the outputs until SO has been brought LOW. 4. When the Master Reset is brought Low, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the Master Reset goes HIGH, the data on the inputs will be written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the Master Reset is ended, IR will go HIGH, but the data in the inputs will not enter the memory until SI goes HIGH. 5. FIFOs are expandable on depth and width. However, in forming wider words, two external gates are required to generate composite Input and Output Ready flags. This is due to the variation of delays of the FIFOs. Figure 11. 192 x 12 Depth and Width Expansion
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IDT72401, IDT72402, IDT72403, IDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX X Power X Speed X Package X Process/ Temperature Range Blank B Commercial (0C to+70C) Military (-55C to+125C) Compliant to MIL-STD-883, Class B Device Type
P D SO 45 35 25 15 10
Plastic DIP (300 mils wide) Ceramic DIP (300 mils wide) Small Outline IC Com'l. Only Com'l. and Mil Com'l. and Mil Com'l. and Mil Com'l. and Mil
Shift Frequency (fs) Speed in MHz
L 72401 72402 72403 72404
Low Power 64 x 4 FIFO 64 x 5 FIFO 64 x 4 FIFO 64 x 5 FIFO
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